K. İREZ Et Al. , "Characteristics of MS-CMOS logic in sub-32nm technologies," GLSVLSI 2010 , New York, United States Of America, pp.393-396, 2010
İREZ, K. Et Al. 2010. Characteristics of MS-CMOS logic in sub-32nm technologies. GLSVLSI 2010 , (New York, United States Of America), 393-396.
İREZ, K., Zukowski, C. A., & Hu, J., (2010). Characteristics of MS-CMOS logic in sub-32nm technologies . GLSVLSI 2010 (pp.393-396). New York, United States Of America
İREZ, KAĞAN, Charles A. Zukowski, And Jiaping Hu. "Characteristics of MS-CMOS logic in sub-32nm technologies," GLSVLSI 2010, New York, United States Of America, 2010
İREZ, KAĞAN Et Al. "Characteristics of MS-CMOS logic in sub-32nm technologies." GLSVLSI 2010 , New York, United States Of America, pp.393-396, 2010
İREZ, K. Zukowski, C. A. And Hu, J. (2010) . "Characteristics of MS-CMOS logic in sub-32nm technologies." GLSVLSI 2010 , New York, United States Of America, pp.393-396.
@conferencepaper{conferencepaper, author={KAĞAN İREZ Et Al. }, title={Characteristics of MS-CMOS logic in sub-32nm technologies}, congress name={GLSVLSI 2010}, city={New York}, country={United States Of America}, year={2010}, pages={393-396} }