Characteristics of MS-CMOS logic in sub-32nm technologies

İREZ K., Zukowski C. A., Hu J.

GLSVLSI 2010, New York, United States Of America, 16 - 18 May 2010, pp.393-396, (Full Text)

  • Publication Type: Conference Paper / Full Text
  • City: New York
  • Country: United States Of America
  • Page Numbers: pp.393-396
  • Karadeniz Technical University Affiliated: No

Abstract

This paper explores the characteristics of Monotonic-Static CMOS and its potential applications in gate leakage reduction in a hypothetical 22nm Bulk-Si technology with significant gate leakage currents. Using test circuits consisting of NAND and NOR logic gates, we performed a comparison among static, monotonic static and domino logic in terms of various properties including power, delay, noise margin and area. Comparisons were done over a wide range of possible transistor widths to fully characterize the tradeoffs for each circuit type. Experimental results show that MS-CMOS has potential advantages in terms of stand-by power, evaluation speed and noise margin in such a technology.